Programmable timing devices must have a basic set of configuration parameters at each power-on of the timing device in order to generate the required timing device output. Typically, at a power-on of a programmable timing device, typically referred to as a “power-on reset,” the timing device receives a configuration at data interface control circuits of the timing device such as an Inter-IC (I2C) interface or a system management bus (SMB) interface. This configuration is loaded into the timing device and is used to control the initial operation of the timing device.
In order to eliminate the need for receiving configuration data at each power-on reset, timing device have been developed that are configured to be connected to external read only memory (ROM) that includes the required timing device configuration. At power-on reset the timing device configuration from the external ROM is loaded into the timing device to control the initial operation of the timing device.
Though use of a timing device configuration stored in an external ROM eliminates the need to program a configuration into the timing device through the data interface control circuits at each power-on reset, there may be a need to use a different configuration from the timing device configuration stored in the external ROM. To meet this need a one-time programmable non-volatile memory (OTP NVM) can be added to the timing device to allow for use of different configurations without requiring programming of a configuration into the timing device through the data interface control circuits at each power-on reset. However, conventional data structures in the OTP and in the RAM limit the flexibility of the system. Hence, there is a need for a method and apparatus that will provide more flexibility in the configuration of the timing device.